Specifications

All fields in the estatus register have read/write access. All fields reset to 0.
When the Nios II processor takes an interrupt, if status.eh is zero (that is, the MMU is in nonexception
mode), the processor copies the contents of the status register to estatus.
Note: If shadow register sets are implemented, and the interrupt requests a shadow register set, the
Nios II processor copies status to sstatus, not to estatus.
For details about the sstatus register, refer to The sstatus Register section.
The exception handler can examine estatus to determine the pre-exception status of the processor.
When returning from an exception, the eret instruction restores the pre-exception value of status. The
instruction restores the pre-exception value by copying either estatus or sstatus back to status,
depending on the value of status.CRS.
Refer to the Exception Processing section for more information.
Related Information
• Exception Processing on page 3-36
• The sstatus Register on page 3-30
The bstatus Register
The bstatus register holds a saved copy of the status register during break exception processing.
Table 3-11: btatus Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved RSIE NMI PRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRS IL IH EH U PIE
All fields in the bstatus register have read/write access. All fields reset to 0.
The Status Control Register Field Description table describes the details of the fields defined in the
bstatus register.
When a break occurs, the value of the status register is copied into bstatus. Using bstatus, the
debugger can restore the status register to the value prior to the break. The bret instruction causes the
processor to copy bstatus back to status. Refer to the Processing a Break section for more information.
Related Information
Processing a Break on page 3-40
The ienable Register
The ienable register controls the handling of internal hardware interrupts. Each bit of the ienable
register corresponds to one of the interrupt inputs, irq0 through irq31. A value of one in bit n means
that the corresponding irqn interrupt is enabled; a bit value of zero means that the corresponding
interrupt is disabled. Refer to the Exception Processing section for more information.
Note:
When the internal interrupt controller is not implemented, the value of the ienable register is
always 0.
3-16
The bstatus Register
NII51003
2015.04.02
Altera Corporation
Programming Model
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