Specifications

Bit Description Access Reset Available
IL IL is the interrupt level field. The IL field controls what
level of external maskable interrupts can be serviced.
The processor services a maskable interrupt only if its
requested interrupt level is greater than IL.
Read/Write 0 EIC interface
only
(7)
IH IH is the interrupt handler mode bit. The processor sets
IH to one when it takes an external interrupt.
Read/Write 0 EIC interface
only
(7)
EH
(6)
EH is the exception handler mode bit. The processor sets
EH to one when an exception occurs (including breaks).
Software clears EH to zero when ready to handle
exceptions again. EH is used by the MMU to determine
whether a TLB miss exception is a fast TLB miss or a
double TLB miss. In systems without an MMU, EH is
always zero.
Read/Write 0 MMU or ECC
only
(7)
U
(6)
U is the user mode bit. When U = 1, the processor
operates in user mode. When U = 0, the processor
operates in supervisor mode. In systems without an
MMU, U is always zero.
Read/Write 0 MMU or MPU
only
(7)
PIE PIE is the processor interrupt-enable bit. When PIE = 0,
internal and maskable external interrupts and
noninterrupt exceptions are ignored. When PIE = 1,
internal and maskable external interrupts can be taken,
depending on the status of the interrupt controller.
Noninterrupt exceptions are unaffected by PIE.
Read/Write 0 Always
Related Information
External Interrupt Controller Interface on page 3-41
The estatus Register
The estatus register holds a saved copy of the status register during nonbreak exception processing.
Table 3-10: estatus Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved RSIE NMI PRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRS IL IH EH U PIE
(5)
The CRS field is read-only. For information about manually changing register sets, refer to the External
Interrupt Controller Interface section.
(6)
The state where both EH and U are one is illegal and causes undefined results.
(7)
When this field is unimplemented, the field value always reads as 0, and the processor behaves accordingly.
(8)
When this field is unimplemented, the field value always reads as 1, and the processor behaves accordingly.
NII51003
2015.04.02
The estatus Register
3-15
Programming Model
Altera Corporation
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