Specifications
Table 3-9: status Control Register Field Descriptions
Bit Description Access Reset Available
RSIE RSIE is the register set interrupt-enable bit. When set to
1, this bit allows the processor to service external
interrupts requesting the register set that is currently in
use. When set to 0, this bit disallows servicing of such
interrupts.
Read/Write 1 EIC interface
and shadow
register sets
only
(8)
NMI NMI is the nonmaskable interrupt mode bit. The
processor sets NMI to 1 when it takes a nonmaskable
interrupt.
Read 0 EIC interface
only
(7)
PRS PRS is the previous register set field. The processor
copies the CRS field to the PRS field upon one of the
following events:
• In a processor with no MMU, on any exception
• In a processor with an MMU, on one of the
following:
Break exception
Nonbreak exception when status.EH is zero
The processor copies CRS to PRS immediately after
copying the status register to estatus, bstatus or
sstatus.
The number of significant bits in the CRS and PRS
fields depends on the number of shadow register sets
implemented in the Nios II core. The value of CRS
and PRS can range from 0 to n-1, where n is the
number of implemented register sets. The processor
core implements the number of significant bits
needed to represent n-1. Unused high-order bits are
always read as 0, and must be written as 0.
1 Ensure that system software writes only valid
register set numbers to the PRS field. Processor
behavior is undefined with an unimplemented
register set number.
Read/Write
0 Shadow
register sets
only
(7)
CRS CRS is the current register set field. CRS indicates which
register set is currently in use. Register set 0 is the
normal register set, while register sets 1 and higher are
shadow register sets. The processor sets CRS to zero on
any noninterrupt exception.
The number of significant bits in the CRS and PRS fields
depends on the number of shadow register sets
implemented in the Nios II core. Unused high-order
bits are always read as 0, and must be written as 0.
Read
(5)
0 Shadow
register sets
only
(7)
3-14
The status Register
NII51003
2015.04.02
Altera Corporation
Programming Model
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