Specifications

Register Name Register Contents
8 pteaddr Refer to The pteaddr Register
Available only when the MMU is present. Otherwise
reserved.
9 tlbacc Refer to The tlbacc Register
Available only when the MMU is present. Otherwise
reserved.
10 tlbmisc Refer to The tlbmisc Register
Available only when the MMU is present. Otherwise
reserved.
11 eccinj Refer to The eccinj Register
Available only when ECC is present.
12 badaddr Refer to The badaddr Register
13 config Refer to The config Register on page 3-23
Available when the MPU or ECC is present. Otherwise
reserved.
14 mpubase Refer to The mpubase Register
Available only when the MPU is present. Otherwise
reserved.
15 mpuacc Refer to The mpuacc Register for MASK variations
table.
Available only when the MPU is present. Otherwise
reserved.
16–31 Reserved Reserved
The following sections describe the nonreserved control registers.
The status Register
The value in the status register determines the state of the Nios II processor. All status bits are set to
predefined values at processor reset. Some bits are exclusively used by and available only to certain
features of the processor, such as the MMU, MPU or external interrupt controller (EIC) interface.
Table 3-8: status Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved RSIE NMI PRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRS IL IH EH U PIE
NII51003
2015.04.02
The status Register
3-13
Programming Model
Altera Corporation
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