Specifications

Register Name Register Contents
13 config Refer to The config Register on page 3-23
Available only when the MPU or ECC is present.
Otherwise reserved.
14 mpubase Refer to The mpubase Register
Available only when the MPU is present. Otherwise
reserved.
15 mpuacc Refer to The mpuacc Register for MASK variations
table.
Available only when the MPU is present. Otherwise
reserved.
16–31 Reserved Reserved
The following sections describe the nonreserved control registers.
Control registers report the status and change the behavior of the processor. Control registers are accessed
differently than the general-purpose registers. The special instructions rdctl and wrctl provide the only
means to read and write to the control registers and are only available in supervisor mode.
Note:
When writing to control registers, all undefined bits must be written as zero.
The Nios II architecture supports up to 32 control registers. All nonreserved control registers have names
recognized by the assembler.
Table 3-7: Control Register Names and Bits
Register Name Register Contents
0 status Refer to The status Register on page 3-13
1 estatus Refer to The estatus Register on page 3-15
2 bstatus Refer to The bstatus Register
3 ienable Internal interrupt-enable bits
The ienable Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
4 ipending Pending internal interrupt bits
The ipending Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
5 cpuid Unique processor identifier
6 Reserved Reserved
7 exception Refer to The exception Register
3-12
Control Registers
NII51003
2015.04.02
Altera Corporation
Programming Model
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