Specifications

Control Registers
Control registers report the status and change the behavior of the processor. Control registers are accessed
differently than the general-purpose registers. The special instructions rdctl and wrctl provide the only
means to read and write to the control registers and are only available in supervisor mode.
Note: When writing to control registers, all undefined bits must be written as zero.
The Nios II architecture supports up to 32 control registers. All nonreserved control registers have names
recognized by the assembler.
Table 3-6: Control Register Names and Bits
Register Name Register Contents
0 status Refer to The status Register on page 3-13
1 estatus Refer to The estatus Register on page 3-15
2 bstatus Refer to The bstatus Register
3 ienable Internal interrupt-enable bits
The ienable Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
4 ipending Pending internal interrupt bits
The ipending Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
5 cpuid Unique processor identifier
6 Reserved Reserved
7 exception Refer to The exception Register
8 pteaddr Refer to The pteaddr Register
Available only when the MMU is present. Otherwise
reserved.
9 tlbacc Refer to The tlbacc Register
Available only when the MMU is present. Otherwise
reserved.
10 tlbmisc Refer to The tlbmisc Register
Available only when the MMU is present. Otherwise
reserved.
11 eccinj Refer to The eccinj Register
Available only when ECC is present.
12 badaddr Refer to The badaddr Register
NII51003
2015.04.02
Control Registers
3-11
Programming Model
Altera Corporation
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