Specifications

The region limit uses a less-than instead of a less-than-or-equal-to comparison because less-than provides
a more efficient implementation. The limit is one bit larger than the address so that full address range may
be included in a range. Defining the region by limit results in slower and larger address range match logic
than defining by size but allows finer granularity in region sizes.
Access Permissions
The access permissions consist of execute permissions for instruction regions and read/write permissions
for data regions. Any instruction that performs a memory access that violates the access permissions
triggers an exception. Additionally, any instruction that performs a memory access that does not match
any region triggers an exception.
Default Cacheability
The default cacheability specifies whether normal load and store instructions access the data cache or
bypass the data cache. The default cacheability is only present for data regions. You can override the
default cacheability by using the ldio or stio instructions. The bit 31 cache bypass feature is available
when the MPU is present.
Refer to the Cache Memory section for more information on cache bypass.
Related Information
Cache Memory on page 3-58
Overlapping Regions
The memory addresses of regions can overlap. Overlapping regions have several uses including placing
markers or small holes inside of a larger region. For example, the stack and heap may be located in the
same region, growing from opposite ends of the address range. To detect stack/heap overflows, you can
define a small region between the stack and heap with no access permissions and assign it a higher
priority than the larger region. Any access attempts to the hole region trigger an exception informing
system software about the stack/heap overflow.
If regions overlap so that a particular access matches more than one region, the region with the highest
priority (lowest index) determines the access permissions and default cacheability.
Enabling the MPU
The MPU is disabled on system reset. System software enables and disables the MPU by writing to a
control register. Before enabling the MPU, you must create at least one instruction and one data region,
otherwise unexpected results can occur. Refer to the Working with the MPU section for more
information.
Related Information
Working with the MPU on page 3-32
Registers
The Nios II register set includes general-purpose registers and control registers. In addition, the Nios II/f
core can optionally have shadow register sets. This section discusses each register type.
NII51003
2015.04.02
Access Permissions
3-9
Programming Model
Altera Corporation
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