Specifications

handle the exception as appropriate. The precise exception effectively prevents the illegal access to
memory.
The MPU extends the Nios II processor to support user mode and supervisor mode. Typically, system
software runs in supervisor mode and end-user applications run in user mode, although all software can
run in supervisor mode if desired. System software defines which MPU regions belong to supervisor
mode and which belong to user mode.
Related Information
Memory Management Unit on page 3-2
Memory Regions
The MPU contains up to 32 instruction regions and 32 data regions. Each region is defined by the
following attributes:
• Base address
• Region type
• Region index
• Region size or upper address limit
• Access permissions
• Default cacheability (data regions only)
Base Address
The base address specifies the lowest address of the region. The base address is aligned on a region-sized
boundary. For example, a 4-KB region must have a base address that is a multiple of 4 KB. If the base
address is not properly aligned, the behavior is undefined.
Region Type
Each region is identified as either an instruction region or a data region.
Region Index
Each region has an index ranging from zero to the number of regions of its region type minus one. Index
zero has the highest priority.
Region Size or Upper Address Limit
A Qsys generation-time option controls whether the amount of memory in the region is defined by size or
upper address limit. The size is an integer power of two bytes. The limit is the highest address of the
region plus one. The minimum supported region size is 64 bytes but can be configured for larger
minimum sizes to save logic resources. The maximum supported region size equals the Nios II address
space (a function of the address ranges of slaves connected to the Nios II masters). Any access outside of
the Nios II address space is considered not to match any region and triggers an MPU region violation
exception.
When regions are defined by size, the size is encoded as a binary mask to facilitate the following MPU
region address range matching:
(address & region_mask) == region_base_address
When regions are defined by limit, the limit is encoded as an unsigned integer to facilitate the following
MPU region address range matching:
(address >= region_base) && (address < region_limit)
3-8
Memory Regions
NII51003
2015.04.02
Altera Corporation
Programming Model
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