Specifications

Related Information
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
TLB Lookups
A TLB lookup attempts to convert a virtual address (VADDR) to a physical address (PADDR).
Example 3-1: TLB Lookup Algorithm for Instruction Fetches
if (VPN match && (G == 1 || PID match))
if (X == 1)
PADDR = concat(PFN, VADDR[11:0])
else take TLB permission violation exception
else
if (EH bit of status register == 1)
take double TLB miss exception
else
take fast TLB miss exception
Example 3-2: TLB Lookup Algorithm for Data Access Operations
if (VPN match && (G == 1 || PID match))
if ((load && R == 1) || (store && W == 1) || flushda)
PADDR = concatenate(PFN, VADDR[11:0])
else
take TLB permission violation exception
else
if (EH bit of status register == 1)
take double TLB miss exception
else
take fast TLB miss exception
Refer to “Instruction-Related Exceptions” for information about TLB exceptions.
Related Information
Instruction-Related Exceptions on page 3-44
Memory Protection Unit
The Nios II processor provides an MPU for operating systems and runtime environments that desire
memory protection but do not require virtual memory management. For information about memory
protection with virtual memory management, refer to the Memory Management Unit section.
When present and enabled, the MPU monitors all Nios II instruction fetches and data memory accesses to
protect against errant software execution. The MPU is a hardware facility that system software uses to
define memory regions and their associated access permissions. The MPU triggers an exception if
software attempts to access a memory region in violation of its permissions, allowing you to intervene and
NII51003
2015.04.02
TLB Lookups
3-7
Programming Model
Altera Corporation
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