Specifications

Whenever an instruction attempts to access a page that either has no TLB mapping, or lacks the
appropriate permissions, the MMU generates an exception. The Nios II processor’s precise exceptions
enable the system software to update the TLB, and then re-execute the instruction if desired.
Memory Protection
The Nios II MMU maintains read, write, and execute permissions for each page. The TLB provides the
permission information when translating a VPN. The operating system can control whether or not each
process is allowed to read data from, write data to, or execute instructions on each particular page. The
MMU also controls whether accesses to each data page are cacheable or uncacheable by default.
Whenever an instruction attempts to access a page that either has no TLB mapping, or lacks the
appropriate permissions, the MMU generates an exception. The Nios II processor’s precise exceptions
enable the system software to update the TLB, and then re-execute the instruction if desired.
Address Space and Memory Partitions
The MMU provides a 4-GB virtual address space, and is capable of addressing up to 4 GB of physical
memory.
Note:
The amount of actual physical memory, determined by the configuration of your hardware system,
might be less than the available 4 GB of physical address space.
Virtual Memory Address Space
The 4-GB virtual memory space is divided into partitions. The upper 2 GB of memory is reserved for the
operating system and the lower 2 GB is reserved for user processes.
Table 3-2: Virtual Memory Partitions
Partition Virtual Address Range Used By Memory Access User Mode
Access
Default Data
Cacheability
I/O 0xE0000000–0xFFFFFFFF Operating
system
Bypasses TLB No Disabled
Kernel 0xC0000000–0xDFFFFFFF Operating
system
Bypasses TLB No Enabled
Kernel
MMU
0x80000000–0xBFFFFFFF Operating
system
Uses TLB No Set by TLB
User 0x00000000–0x7FFFFFFF User processes Uses TLB Set by TLB Set by TLB
Note: All partitions except the user partition in the "Virtual Memory Partition" table are supervisor-only
partitions.
Each partition has a specific size, purpose, and relationship to the TLB:
• The 512-MB I/O partition provides access to peripherals.
• The 512-MB kernel partition provides space for the operating system kernel.
• The 1-GB kernel MMU partition is used by the TLB miss handler and kernel processes.
• The 2-GB user partition is used by application processes.
I/O and kernel partitions bypass the TLB. The kernel MMU and user partitions use the TLB. If all
software runs in the kernel partition, the MMU is effectively disabled.
3-4
Memory Protection
NII51003
2015.04.02
Altera Corporation
Programming Model
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