Specifications

tion’s access to memory and peripherals. In systems with an MPU, your system software controls the
mode in which your application code runs. In Nios II systems without an MMU or MPU, all application
and system code runs in supervisor mode.
Code that needs direct access to and control of the processor runs in supervisor mode. For example, the
processor enters supervisor mode whenever a processor exception (including processor reset or break)
occurs. Software debugging tools also use supervisor mode to implement features such as breakpoints and
watchpoints.
Note: For systems without an MMU or MPU, all code runs in supervisor mode.
User Mode
User mode is available only when the Nios II processor in your hardware design includes an MMU or
MPU. User mode exists solely to support operating systems. Operating systems (that make use of the
processor’s user mode) run your application code in user mode. The user mode capabilities of the
processor are a subset of the supervisor mode capabilities. Only a subset of the instruction set is available
in user mode.
The operating system determines which memory addresses are accessible to user mode applications.
Attempts by user mode applications to access memory locations without user access enabled are not
permitted and cause an exception. Code running in user mode uses system calls to make requests to the
operating system to perform I/O operations, manage memory, and access other system functionality in
the supervisor memory.
The Nios II MMU statically divides the 32-bit virtual address space into user and supervisor partitions.
Refer to Address Space and Memory Partitions section for more information about the MMU memory
partitions. The MMU provides operating systems access permissions on a per-page basis. Refer to Virtual
Addressing for more information about MMU pages.
The Nios II MPU supervisor and user memory divisions are determined by the operating system or
runtime environment. The MPU provides user access permissions on a region basis. Refer to Memory
Regions for more information about MPU regions.
Related Information
• Address Space and Memory Partitions on page 3-4
• Memory Regions on page 3-8
• Virtual Addressing on page 3-3
Memory Management Unit
The Nios II processor provides an MMU to support full-featured operating systems. Operating systems
that require virtual memory rely on an MMU to manage the virtual memory. When present, the MMU
manages memory accesses including translation of virtual addresses to physical addresses, memory
protection, cache control, and software process memory allocation.
Recommended Usage
Including the Nios II MMU in your Nios II hardware system is optional. The MMU is only useful with an
operating system that takes advantage of it.
Many Nios II systems have simpler requirements where minimal system software or a small-footprint
operating system (such as the Altera
®
hardware abstraction library (HAL) or a third party real-time
operating system) is sufficient. Such software is unlikely to function correctly in a hardware system with
3-2
User Mode
NII51003
2015.04.02
Altera Corporation
Programming Model
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