Specifications
No-Operation Instruction............................................................................................................ 3-65
Potential Unimplemented Instructions......................................................................................3-65
Document Revision History.....................................................................................................................3-66
Instantiating the Nios II Processor.....................................................................4-1
Core Nios II Tab...........................................................................................................................................4-1
Core Selection...................................................................................................................................4-2
Multiply and Divide Settings..........................................................................................................4-3
Reset Vector......................................................................................................................................4-3
General Exception Vector...............................................................................................................4-4
Memory Management Unit Settings.............................................................................................4-4
Memory Protection Unit Settings..................................................................................................4-5
Caches and Memory Interfaces Tab..........................................................................................................4-5
Instruction Master Settings............................................................................................................ 4-6
Data Master Settings........................................................................................................................4-7
Advanced Features Tab...............................................................................................................................4-7
Reset Signals......................................................................................................................................4-8
Control Registers..............................................................................................................................4-8
Exception Checking.........................................................................................................................4-9
Interrupt Controller Interfaces.................................................................................................... 4-10
Shadow Register Sets..................................................................................................................... 4-10
HardCopy Compatible..................................................................................................................4-10
ECC..................................................................................................................................................4-11
MMU and MPU Settings Tab.................................................................................................................. 4-11
MMU............................................................................................................................................... 4-12
MPU.................................................................................................................................................4-12
JTAG Debug Module Tab.........................................................................................................................4-13
Debug Level Settings......................................................................................................................4-14
Debug Signals................................................................................................................................. 4-15
Break Vector...................................................................................................................................4-15
Advanced Debug Settings.............................................................................................................4-16
Custom Instruction Tab............................................................................................................................4-16
Altera-Provided Custom Instructions........................................................................................ 4-16
The Quartus II IP File................................................................................................................................4-18
Document Revision History.....................................................................................................................4-19
Nios II Core Implementation Details.................................................................5-1
Device Family Support................................................................................................................................5-3
Nios II/f Core................................................................................................................................................5-3
Overview............................................................................................................................................5-4
Arithmetic Logic Unit..................................................................................................................... 5-4
Memory Access................................................................................................................................ 5-6
Tightly-Coupled Memory...............................................................................................................5-9
Memory Management Unit............................................................................................................5-9
Memory Protection Unit.............................................................................................................. 5-10
Execution Pipeline.........................................................................................................................5-10
Instruction Performance...............................................................................................................5-11
TOC-4
Altera Corporation