Specifications

Date Version Changes
December 2010 10.1.0 Added reference to tightly-coupled memory tutorial.
July 2010 10.0.0 Maintenance release.
November 2009 9.1.0
• Added external interrupt controller interface information.
• Added shadow register set information.
March 2009 9.0.0 Maintenance release.
November 2008 8.1.0
• Expanded floating-point instructions information.
• Updated description of optional cpu_resetrequest and cpu_
resettaken signals.
• Added description of optional debugreq and debugack signals.
May 2008 8.0.0 Added MMU and MPU sections.
October 2007 7.2.0 Maintenance release.
May 2007 7.1.0
• Added table of contents to Introduction section.
• Added Referenced Documents section.
March 2007 7.0.0 Maintenance release.
November 2006 6.1.0 Described interrupt vector custom instruction.
May 2006 6.0.0
• Added description of optional cpu_resetrequest and cpu_
resettaken.
• Added section on single precision floating-point instructions.
October 2005 5.1.0 Maintenance release.
May 2005 5.0.0 Added tightly-coupled memory.
December 2004 1.2 Added new control register ctl5.
September 2004 1.1 Updates for Nios II 1.01 release.
May 2004 1.0 Initial release.
2-24
Document Revision History
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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