Specifications

Execution vs. Data Trace
The JTAG debug module supports tracing the instruction bus (execution trace), the data bus (data trace),
or both simultaneously. Execution trace records only the addresses of the instructions executed, enabling
you to analyze where in memory (that is, in which functions) code executed. Data trace records the data
associated with each load and store operation on the data bus.
The JTAG debug module can filter the data bus trace in real time to capture the following:
• Load addresses only
• Store addresses only
• Both load and store addresses
• Load data only
• Load address and data
• Store address and data
• Address and data for both loads and stores
• Single sample of the data bus upon trigger event
Trace Frames
A frame is a unit of memory allocated for collecting trace data. However, a frame is not an absolute
measure of the trace depth.
To keep pace with the processor executing in real time, execution trace is optimized to store only selected
addresses, such as branches, calls, traps, and interrupts. From these addresses, host-side debug software
can later reconstruct an exact instruction-by-instruction execution trace. Furthermore, execution trace
data is stored in a compressed format, such that one frame represents more than one instruction. As a
result of these optimizations, the actual start and stop points for trace collection during execution might
vary slightly from the user-specified start and stop points.
Data trace stores 100% of requested loads and stores to the trace buffer in real time. When storing to the
trace buffer, data trace frames have lower priority than execution trace frames. Therefore, while data
frames are always stored in chronological order, execution and data trace are not guaranteed to be exactly
synchronized with each other.
Document Revision History
Table 2-7: Document Revision History
Date Version Changes
April 2015 2015.04.02 Maintenance release.
February 2014 13.1.0
• Added information on ECC support.
• Added information on enhanced floating-point custom instruc‐
tions.
• Removed HardCopy information.
• Removed references to SOPC Builder.
May 2011 11.0.0
• Added references to new Qsys system integration tool.
• Moved interrupt vector custom instruction information to the
Instantiating the Nios II Processor chapter.
NII51002
2015.04.02
Execution vs. Data Trace
2-23
Processor Architecture
Altera Corporation
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