Specifications

Table 2-6: Trigger Actions
Action Description
Break Halt execution and transfer control to the JTAG debug module.
External trigger Assert a trigger signal output. This trigger output can be used, for example, to
trigger an external logic analyzer.
Trace on Turn on trace collection.
Trace off Turn off trace collection.
Trace sample Store one sample of the bus to trace buffer.
Arm Enable an armed trigger.
Note: For the Trace sample triger action, only conditions on the data bus can trigger this action.
Armed Triggers
The JTAG debug module provides a two-level trigger capability, called armed triggers. Armed triggers
enable the JTAG debug module to trigger on event B, only after event A. In this example, event A causes a
trigger action that enables the trigger for event B.
Triggering on Ranges of Values
The JTAG debug module can trigger on ranges of data or address values on the data bus. This mechanism
uses two hardware triggers together to create a trigger condition that activates on a range of values within
a specified range.
Trace Capture
Trace capture refers to ability to record the instruction-by-instruction execution of the processor as it
executes code in real-time. The JTAG debug module offers the following trace features:
• Capture execution trace (instruction bus cycles).
• Capture data trace (data bus cycles).
• For each data bus cycle, capture address, data, or both.
• Start and stop capturing trace in real time, based on triggers.
• Manually start and stop trace under host control.
• Optionally stop capturing trace when trace buffer is full, leaving the processor executing.
• Store trace data in on-chip memory buffer in the JTAG debug module. (This memory is accessible only
through the JTAG connection.)
• Store trace data to larger buffers in an off-chip debug probe.
Certain trace features require additional licensing or debug tools from third-party debug providers. For
example, an on-chip trace buffer is a standard feature of the Nios II processor, but using an off-chip trace
buffer requires additional debug software and hardware provided by Imagination Technologies
™
, LLC or
Lauterbach GmbH.
Related Information
Lauterbach.com
For more information, refer to the Lauterbach GmbH website.
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Armed Triggers
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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