Specifications

• Hardware translation lookaside buffers (TLBs), accelerating address translation
• Separate TLBs for instruction and data accesses
• Read, write, and execute permissions controlled per page
• Default caching behavior controlled per page
• TLBs acting as n-way set-associative caches for software page tables
• TLB sizes and associativities configurable in the Nios II Processor parameter editor
• Format of page tables (or equivalent data structures) determined by system software
• Replacement policy for TLB entries determined by system software
• Write policy for TLB entries determined by system software
For more information about the MMU implementation, refer to the Programming Model chapter of the
Nios II Processor Reference Handbook.
You can optionally include the MMU when you instantiate the Nios II processor in your Nios II hardware
system. When present, the MMU is always enabled, and the data and instruction caches are virtually-
indexed, physically-tagged caches. Several parameters are available, allowing you to optimize the MMU
for your system needs.
For complete details about user-selectable parameters for the Nios II MMU, refer to the Instantiating the
Nios II Processor chapter of the Nios II Processor Reference Handbook.
Note:
The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II systems can
include either an MMU or MPU, but cannot include both an MMU and MPU on the same Nios II
processor core.
Related Information
• Programming Model on page 3-1
• Programming Model
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
Memory Protection Unit
The optional Nios II MPU provides the following features and functionality:
• Memory protection
• Up to 32 instruction regions and 32 data regions
• Variable instruction and data region sizes
• Amount of region memory defined by size or upper address limit
• Read and write access permissions for data regions
• Execute access permissions for instruction regions
• Overlapping regions
For more information about the MPU implementation, refer to the Programming Model chapter of the
Nios II Processor Reference Handbook.
You can optionally include the MPU when you instantiate the Nios II processor in your Nios II hardware
system. When present, the MPU is always enabled. Several parameters are available, allowing you to
optimize the MPU for your system needs.
For complete details about user-selectable parameters for the Nios II MPU, refer to the Instantiating the
Nios II Processor chapter of the Nios II Processor Reference Handbook.
NII51002
2015.04.02
Memory Protection Unit
2-19
Processor Architecture
Altera Corporation
Send Feedback