Specifications

Accessing Tightly-Coupled Memory
Tightly-coupled memories occupy normal address space, the same as other memory devices connected via
system interconnect fabric. The address ranges for tightly-coupled memories (if any) are determined at
system generation time.
Software accesses tightly-coupled memory using regular load and store instructions. From the software’s
perspective, there is no difference accessing tightly-coupled memory compared to other memory.
Effective Use of Tightly-Coupled Memory
A system can use tightly-coupled memory to achieve maximum performance for accessing a specific
section of code or data. For example, interrupt-intensive applications can place exception handler code
into a tightly-coupled memory to minimize interrupt latency. Similarly, compute-intensive digital signal
processing (DSP) applications can place data buffers into tightly-coupled memory for the fastest possible
data access.
If the application’s memory requirements are small enough to fit entirely on chip, it is possible to use
tightly-coupled memory exclusively for code and data. Larger applications must selectively choose what to
include in tightly-coupled memory to maximize the cost-performance trade-off.
Related Information
Using Tightly Coupled Memory with the Nios II Processor Tutorial
For additional tightly-coupled memory guidelines, refer to the Using Tightly Coupled Memory with the
Nios II Processor tutorial.
Address Map
The address map for memories and peripherals in a Nios II processor system is design dependent. You
specify the address map in Qsys.
There are three addresses that are part of the processor and deserve special mention:
• Reset address
• Exception address
• Break handler address
Programmers access memories and peripherals by using macros and drivers. Therefore, the flexible
address map does not affect application developers.
Memory Management Unit
The optional Nios II MMU provides the following features and functionality:
• Virtual to physical address mapping
• Memory protection
• 32-bit virtual and physical addresses, mapping a 4-GB virtual address space into as much as 4 GB of
physical memory
• 4-KB page and frame size
• Low 512 MB of physical address space available for direct access
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Accessing Tightly-Coupled Memory
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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