Specifications

Optimal cache configuration is application specific, although you can make decisions that are effective
across a range of applications. For example, if a Nios II processor system includes only fast, on-chip
memory (i.e., it never accesses slow, off-chip memory), an instruction or data cache is unlikely to offer any
performance gain. As another example, if the critical loop of a program is 2 KB, but the size of the instruc‐
tion cache is 1 KB, an instruction cache does not improve execution speed. In fact, an instruction cache
may degrade performance in this situation.
If an application always requires certain data or sections of code to be located in cache memory for
performance reasons, the tightly-coupled memory feature might provide a more appropriate solution.
Refer to the "Tightly-Coupled Memory" section for details.
Cache Bypass Methods
The Nios II architecture provides the following methods for bypassing the data cache:
• I/O load and store instructions
• Bit-31 cache bypass
I/O Load and Store Instructions Method
The load and store I/O instructions such as ldio and stio bypass the data cache and force an Avalon-
MM data transfer to a specified address.
The Bit-31 Cache Bypass Method
The bit-31 cache bypass method on the data master port uses bit 31 of the address as a tag that indicates
whether the processor should transfer data to/from cache, or bypass it. This is a convenience for software,
which might need to cache certain addresses and bypass others. Software can pass addresses as parameters
between functions, without having to specify any further information about whether the addressed data is
cached or not.
To determine which cores implement which cache bypass methods, refer to the Nios II Core Implementa‐
tion Details chapter of the Nios II Processor Reference Handbook.
Related Information
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
Tightly-Coupled Memory
Tightly-coupled memory provides guaranteed low-latency memory access for performance-critical
applications. Compared to cache memory, tightly-coupled memory provides the following benefits:
• Performance similar to cache memory
• Software can guarantee that performance-critical code or data is located in tightly-coupled memory
• No real-time caching overhead, such as loading, invalidating, or flushing memory
Physically, a tightly-coupled memory port is a separate master port on the Nios II processor core, similar
to the instruction or data master port. A Nios II core can have zero, one, or multiple tightly-coupled
memories. The Nios II architecture supports tightly-coupled memory for both instruction and data
access. Each tightly-coupled memory port connects directly to exactly one memory with guaranteed low,
fixed latency. The memory is external to the Nios II core and is located on chip.
NII51002
2015.04.02
Cache Bypass Methods
2-17
Processor Architecture
Altera Corporation
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