Specifications

Figure 2-2: Nios II Memory and I/O Organization
S
Memory
S
Slave
Peripheral
Avalon Master Port
Avalon Slave Port
M
S
M
M
Tightly Coupled
Instruction
Memory N
Tightly Coupled
Data
Memory 1
Instruction
Cache
Data
Cache
Avalon System
Interconnect
Fabric
Program
Counter
General
Purpose
Register
File
Instruction
Bus
Selector
Logic
Tightly Coupled
Data
Memory N
Tightly Coupled
Instruction
Memory 1
Data
Bus
Selector
Logic
MMU
Translation
Lookaside Buffer
M
M
M
M
Data
Cache
Bypass
Logic
MPU Instruction Regions
MPU Data Regions
Related Information
• Programming Model on page 3-1
• Programming Model
Instruction and Data Buses
The Nios II architecture supports separate instruction and data buses, classifying it as a Harvard architec‐
ture. Both the instruction and data buses are implemented as Avalon-MM master ports that adhere to the
Avalon-MM interface specification. The data master port connects to both memory and peripheral
components, while the instruction master port connects only to memory components.
2-14
Instruction and Data Buses
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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