Specifications

A Nios II core uses one or more of the following to provide memory and I/O access:
Instruction master port—An Avalon
®
Memory-Mapped (Avalon-MM) master port that connects to
instruction memory via system interconnect fabric
Instruction cache—Fast cache memory internal to the Nios II core
Data master port—An Avalon-MM master port that connects to data memory and peripherals via
system interconnect fabric
Data cache—Fast cache memory internal to the Nios II core
Tightly-coupled instruction or data memory port—Interface to fast on-chip memory outside the
Nios II core
The Nios II architecture handles the hardware details for the programmer, so programmers can develop
Nios II applications without specific knowledge of the hardware implementation.
For details that affect programming issues, refer to the Programming Model chapter of the Nios II
Processor Reference Handbook.
NII51002
2015.04.02
Memory and I/O Organization
2-13
Processor Architecture
Altera Corporation
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