Specifications

An EIC can be software-configurable.
Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you must
ensure that your software is built with the Nios II EDS version 9.0 or higher. Earlier versions have
an implementation of the eret instruction that is incompatible with shadow register sets.
For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the Embedded
Peripherals IP User Guide.
For details about EIC usage, refer to “Exception Processing” in the Programming Model chapter of the
Nios II Processor Reference Handbook.
Related Information
• Embedded Peripherals IP User Guide
For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the Embedded
Peripherals IP User Guide.
• Programming Model on page 3-1
• Programming Model
Internal Interrupt Controller
The Nios II architecture supports 32 internal hardware interrupts. The processor core has 32 level-
sensitive interrupt request (IRQ) inputs, irq0 through irq31, providing a unique input for each interrupt
source. IRQ priority is determined by software. The architecture supports nested interrupts.
Your software can enable and disable any interrupt source individually through the ienable control
register, which contains an interrupt-enable bit for each of the IRQ inputs. Software can enable and
disable interrupts globally using the PIE bit of the status control register. A hardware interrupt is
generated if and only if all of the following conditions are true:
• The PIE bit of the status register is 1
• An interrupt-request input, irq<n>, is asserted
• The corresponding bit n of the ienable register is 1
The interrupt vector custom instruction is less efficient than using the EIC interface with the Altera
vectored interrupt controller component, and thus is deprecated in Qsys. Altera recommends using the
EIC interface.
Memory and I/O Organization
This section explains hardware implementation details of the Nios II memory and I/O organization. The
discussion covers both general concepts true of all Nios II processor systems, as well as features that might
change from system to system.
The flexible nature of the Nios II memory and I/O organization are the most notable difference between
Nios II processor systems and traditional microcontrollers. Because Nios II processor systems are
configurable, the memories and peripherals vary from system to system. As a result, the memory and I/O
organization varies from system to system.
2-12
Internal Interrupt Controller
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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