Specifications

Instruction Type
R
Instruction Fields
None
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0x36
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x36 0 0x3a
trap
Instruction
trap
Operation
estatus ← status
PIE ← 0
U ← 0
ea ← PC + 4
PC ← exception handler address
Assembler Syntax
trap
trap imm5
Example
trap
Description
Saves the address of the next instruction in register ea, saves
the contents of the status register in estatus, disables
interrupts, and transfers execution to the exception handler.
The address of the exception handler is specified with the Nios_
II Processor parameter editor in Qsys.
The 5-bit immediate field imm5 is ignored by the processor, but
it can be used by the debugger.
trap with no argument is the same as trap 0.
Usage
To return from the exception handler, execute an eret instruc‐
tion.
Exceptions
Trap
Instruction Type
R
Instruction Fields
IMM5 = Type of breakpoint
NII51017
2015.04.02
trap
8-81
Instruction Set Reference
Altera Corporation
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