Specifications

Description
Computes the effective byte address specified by the sum of rA
and the instruction's signed 16-bit immediate value. Stores rB
to the memory location specified by the effective byte address.
The effective byte address must be word aligned. If the byte
address is not a multiple of 4, the operation is undefined.
Usage
In processors with a data cache, this instruction may not
generate an Avalon-MM data transfer immediately. Use the
stwio instruction for peripheral I/O. In processors with a data
cache, stwio bypasses the cache and is guaranteed to generate
an Avalon-MM bus cycle. In processors without a data cache,
stwio acts like stw.
Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
Table 8-23: stw
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x15
Table 8-24: stwio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x35
NII51017
2015.04.02
stw / stwio
8-77
Instruction Set Reference
Altera Corporation
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