Specifications

Signal Name Type Purpose
reset_req Reset This optional signal prevents the memory corruption by performing a
reset handshake before the processor resets.
For more information on adding reset signals to the Nios II processor, refer to “Advanced Features Tab”
in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook.
For more information on the break vector and adding debug signals to the Nios II processor, refer to
“JTAG Debug Module Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor
Reference Handbook.
Related Information
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
Exception and Interrupt Controllers
The Nios II processor includes hardware for handling exceptions, including hardware interrupts. It also
includes an optional external interrupt controller (EIC) interface. The EIC interface enables you to speed
up interrupt handling in a complex system by adding a custom interrupt controller.
Exception Controller
The Nios II architecture provides a simple, nonvectored exception controller to handle all exception types.
Each exception, including internal hardware interrupts, causes the processor to transfer execution to an
exception address. An exception handler at this address determines the cause of the exception and
dispatches an appropriate exception routine.
Exception addresses are specified with the Qsys Nios II Processor parameter editor.
All exceptions are precise. Precise means that the processor has completed execution of all instructions
preceding the faulting instruction and not started execution of instructions following the faulting instruc‐
tion. Precise exceptions allow the processor to resume program execution once the exception handler
clears the exception.
EIC Interface
An EIC provides high performance hardware interrupts to reduce your program's interrupt latency. An
EIC is typically used in conjunction with shadow register sets and when you need more than the 32
interrupts provided by the Nios II internal interrupt controller.
The Nios II processor connects to an EIC through the EIC interface. When an EIC is present, the internal
interrupt controller is not implemented; Qsys connects interrupts to the EIC.
The EIC selects among active interrupts and presents one interrupt to the Nios II processor, with
interrupt handler address and register set selection information. The interrupt selection algorithm is
specific to the EIC implementation, and is typically based on interrupt priorities. The Nios II processor
does not depend on any specific interrupt prioritization scheme in the EIC.
For every external interrupt, the EIC presents an interrupt level. The Nios II processor uses the interrupt
level in determining when to service the interrupt.
Any external interrupt can be configured as an NMI. NMIs are not masked by the status.PIE bit, and
have no interrupt level.
NII51002
2015.04.02
Exception and Interrupt Controllers
2-11
Processor Architecture
Altera Corporation
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