Specifications

Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
Table 8-21: sth
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x0d
Table 8-22: sthio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x2d
stw / stwio
Instruction
store word to memory or I/O peripheral
Operation
Mem32[rA + σ(IMM16)] ← rB
Assembler Syntax
stw rB, byte_offset(rA)
stwio rB, byte_offset(rA)
Example
stw r6, 100(r5)
8-76
stw / stwio
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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