Specifications
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
Table 8-19: stb
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x05
Table 8-20: stbio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x25
sth / sthio
Instruction
store halfword to memory or I/O peripheral
Operation
Mem16[rA + σ(IMM16)] ← rB
15..0
Assembler Syntax
sth rB, byte_offset(rA)
sthio rB, byte_offset(rA)
Example
sth r6, 100(r5)
Description
Computes the effective byte address specified by the sum of rA
and the instruction's signed 16-bit immediate value. Stores the
low halfword of rB to the memory location specified by the
effective byte address. The effective byte address must be
halfword aligned. If the byte address is not a multiple of 2, the
operation is undefined.
Usage
In processors with a data cache, this instruction may not
generate an Avalon-MM data transfer immediately. Use the
sthio instruction for peripheral I/O. In processors with a data
cache, sthio bypasses the cache and is guaranteed to generate
an Avalon-MM data transfer. In processors without a data
cache, sthio acts like sth.
NII51017
2015.04.02
sth / sthio
8-75
Instruction Set Reference
Altera Corporation
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