Specifications

Instruction Fields
A = Register index of operand rA
C = Register index of operand rC
IMM5 = 5-bit unsigned immediate value
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B C 0x1a
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x1a IMM5 0x3a
stb / stbio l
Instruction
store byte to memory or I/O periphera
Operation
Mem8[rA + σ(IMM16)] ← rB
7..0
Assembler Syntax
stb rB, byte_offset(rA)
stbio rB, byte_offset(rA)
Example
stb r6, 100(r5)
Description
Computes the effective byte address specified by the sum of rA
and the instruction's signed 16-bit immediate value. Stores the
low byte of rB to the memory byte specified by the effective
address.
Usage
In processors with a data cache, this instruction may not
generate an Avalon-MM bus cycle to noncache data memory
immediately. Use the stbio instruction for peripheral I/O. In
processors with a data cache, stbio bypasses the cache and is
guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache, stbio acts like stb.
Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
8-74
stb / stbio l
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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