Specifications

In Qsys, the Floating Point Hardware component is under Embedded Processors on the Component
Library tab.
The Nios II floating-point custom instructions are based on the Altera
®
floating-point megafunctions:
ALTFP_MULT, ALTFP_ADD_SUB, and ALTFP_DIV.
The Nios II software development tools recognize C code that takes advantage of the floating-point
instructions present in the processor core. When the floating-point custom instructions are present in
your target hardware, the Nios II compiler compiles your code to use the custom instructions for floating-
point operations and the newlib math library.
Related Information
IP and Megafunctions
For information about each individual floating-point megafunction, including acceleration factors and
device resource usage, refer to the megafunction user guides, available on the IP and Megafunctions
literature page of the Altera website.
Reset and Debug Signals
The table below describes the reset and debug signals that the Nios II processor core supports.
Table 2-4: Nios II Processor Debug and Reset Signals
Signal Name Type Purpose
reset Reset This is a global hardware reset signal that forces the processor core to
reset immediately.
cpu_resetrequest Reset This is an optional, local reset signal that causes the processor to reset
without affecting other components in the Nios II system. The
processor finishes executing any instructions in the pipeline, and then
enters the reset state. This process can take several clock cycles, so be
sure to continue asserting the cpu_resetrequest signal until the
processor core asserts a cpu_resettaken signal.
The processor core asserts a cpu_resettaken signal for 1 cycle when
the reset is complete and then periodically if cpu_resetrequest
remains asserted. The processor remains in the reset state for as long
as cpu_resetrequest is asserted. While the processor is in the reset
state, it periodically reads from the reset address. It discards the result
of the read, and remains in the reset state.
The processor does not respond to cpu_resetrequest when the
processor is under the control of the JTAG debug module, that is,
when the processor is paused. The processor responds to the cpu_
resetrequest signal if the signal is asserted when the JTAG debug
module relinquishes control, both momentarily during each single
step as well as when you resume execution.
debugreq
Debug This is an optional signal that temporarily suspends the processor for
debugging purposes. When you assert the signal, the processor pauses
in the same manner as when a breakpoint is encountered, transfers
execution to the routine located at the break address, and asserts a
debugack signal. Asserting the debugreq signal when the processor is
already paused has no effect.
2-10
Reset and Debug Signals
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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