Specifications

Operation
(2)
N
(3)
Cycles Result Subnormal Rounding GCC
Inference
floatis 250 4 int_to_float(a) Not
applicable
Not
applicable
Casting
fixsi 249 2 float_to_int(a) Flush to 0 Truncation Casting
round 248 2 float_to_int(a) Flush to 0 Nearest lroundf()
(
4)
Reserved 234 to 247 Undefined Undefined
fmins 233 1 (a < b) ? a : b Supported None fminf()
(4)
fmaxs 232 1 (a < b) ? b : a Supported None fmaxf()
(4)
fcmplts 231 1 (a < b) ? 1 : 0 Supported None a < b
fcmples 230 1 (a ≤ b) ? 1 : 0 Supported None a <= b
fcmpgts 229 1 (a > b) ? 1 : 0 Supported None a > b
fcmpges 228 1 (a ≥ b) ? 1 : 0 Supported None a >= b
fcmpeqs 227 1 (a = b) ? 1 : 0 Supported None a == b
fcmpnes 226 1 (a ≠ b) ? 1 : 0 Supported None a != b
fnegs 225 1 -a Supported None -a
fabss 224 1 |a| Supported None fabsf()
The cycles column specifies the number of cycles required to execute the instruction. A combinatorial
custom instruction takes 1 cycle. A multi-cycle custom instruction requires at least 2 cycles. An N-cycle
multi-cycle custom instruction has N - 2 register stages inside the custom instruction because the Nios II
processor registers the result from the custom instruction and allows another cycle for g wire delays in the
source operand bypass multiplexers. The number of cycles does not include the extra cycles (maximum of
2) that an instruction following the multi-cycle custom instruction is stalled by the Nios II/f if the instruc‐
tion uses the result within 2 cycles. These extra cycles occur because multi-cycle instructions are late result
instructions
In Qsys, the Floating Point Hardware 2 component is under Embedded Processors on the Component
Library tab.
The Nios II Software Build Tools (SBT) include software support for the Floating Point Custom Instruc‐
tion 2 component. When the Floating Point Custom Instruction 2 component is present in hardware, the
Nios II compiler compiles the software codes to use the custom instructions for floating point operations.
Floating Point Custom Instruction Component
The Floating Point Hardware component supports addition, subtraction, multiplication, and (optionally)
division. The Floating Point Hardware parameter editor allows you to omit the floating-point division
hardware for cases in which code running on your hardware design does not make heavy use of floating-
point division. When you omit the floating-point divide instruction, the Nios II compiler implements
floating-point division in software.
(2)
These names match the names of the corresponding GCC command-line options except for round, which
GCC does not support.
(3)
Specifies the 8 bit fixed custom instruction for the operation.
NII51002
2015.04.02
Floating Point Custom Instruction Component
2-9
Processor Architecture
Altera Corporation
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