Specifications

Description
Computes the effective byte address specified by the sum of rA
and the instruction's signed 16-bit immediate value. Loads
register rB with the memory word located at the effective byte
address. The effective byte address must be word aligned. If the
byte address is not a multiple of 4, the operation is undefined.
Usage
In processors with a data cache, this instruction may retrieve
the desired data from the cache instead of from memory. Use
the ldwio instruction for peripheral I/O. In processors with a
data cache, ldwio bypasses the cache and memory. Use the
ldwio instruction for peripheral I/O. In processors with a data
cache, ldwio bypasses the cache and is guaranteed to generate
an Avalon-MM data transfer. In processors without a data
cache, ldwio acts like ldw.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
Table 8-17: ldw
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x17
Table 8-18: ldwio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
8-54
ldw / ldwio
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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