Specifications

Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
Table 8-15: ldhu
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x0b
Table 8-16: ldhuio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x2b
Related Information
Cache and Tightly-Coupled Memory
ldw / ldwio
Instruction
load 32-bit word from memory or I/O peripheral
Operation
rB ← Mem32[rA + σ(IMM14)]
Assembler Syntax
ldw rB, byte_offset(rA)
ldwio rB, byte_offset(rA)
Example
ldw r6, 100(r5)
NII51017
2015.04.02
ldw / ldwio
8-53
Instruction Set Reference
Altera Corporation
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