Specifications

Bit Fields
IMM16 0x23
Related Information
Cache and Tightly-Coupled Memory
ldh / ldhio
Instruction load halfword from memory or I/O peripheral
Operation
rB ← σ(Mem16[rA + σ(IMM16)])
Assembler Syntax
ldh rB, byte_offset(rA)
ldhio rB, byte_offset(rA)
Example
ldh r6, 100(r5)
Description
Computes the effective byte address specified by the sum of rA
and the instruction's signed 16-bit immediate value. Loads
register rB with the memory halfword located at the effective
byte address, sign extending the 16-bit value to 32 bits. The
effective byte address must be halfword aligned. If the byte
address is not a multiple of 2, the operation is undefined.
Usage
In processors with a data cache, this instruction may retrieve
the desired data from the cache instead of from memory. Use
the ldhio instruction for peripheral I/O. In processors with a
data cache, ldhio bypasses the cache and is guaranteed to
generate an Avalon-MM data transfer. In processors without a
data cache, ldhio acts like ldh.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
Exceptions
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Instruction Type
I
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
NII51017
2015.04.02
ldh / ldhio
8-51
Instruction Set Reference
Altera Corporation
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