Specifications
Related Information
Nios II Custom Instruction User Guide
For more information about using floating-point custom instructions in software, refer to the Nios II
Custom Instruction User Guide.
Floating Point Custom Instruction 2 Component
You can add floating-point custom instructions to any Nios II processor design. The floating-point
division hardware requires more resources than the other instructions. The Floating Point Hardware 2
component supports the following single-precision floating-point operations:
• Add
• Subtract
• Multiply
• Divide
• Square root
• Comparison
• Integer conversion
• Minimum
• Maximum
• Negate
• Absolute
Other floating-point operations (including double-precision operations) are implemented with software
emulation. The component requires the following device resources:
• ~2,500 4-input LEs
• 9 x 9 bit multipliers
• 3x M9K memories
In the following table, a and b are assumed to be single-precision floating-point values.
Table 2-3: Floating Point Custom Instruction 2 Operation Summary
Operation
(2)
N
(3)
Cycles Result Subnormal Rounding GCC
Inference
fdivs 255 16 a ÷ b Flush to 0 Nearest a / b
fsubs 254 5 a – b Flush to 0 Faithful a – b
fadds 253 5 a + b Flush to 0 Faithful a + b
fmuls 252 4 a x b Flush to 0 Faithful a * b
fsqrts 251 8
a
Flush to 0 Faithful sqrtf()
(4)
(2)
These names match the names of the corresponding GCC command-line options except for round, which
GCC does not support.
(3)
Specifies the 8 bit fixed custom instruction for the operation.
(4)
Nios II GCC version 4.7.3 is not able to reliably replace calls to newlib floating-point functions with the
equivalent custom instruction even though it has -mcustom-<operation> command-line options and
pragma support for these operations. Instead, the custom instruction must be invoked directly using the
GCC __builtin_custom_* facility. The Floating Point Custom Instruction 2 component includes a C
header file that provides the required #define macros to invoke the custom instruction directly.
2-8
Floating Point Custom Instruction 2 Component
NII51002
2015.04.02
Altera Corporation
Processor Architecture
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