Specifications

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A 0 IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x13
Related Information
• Cache and Tightly-Coupled Memory
• flushda on page 8-40
• initd on page 8-43
• flushd on page 8-38
initi
Instruction
initialize instruction cache line
Operation
Initializes the instruction cache line associated with address rA.
Assembler Syntax
initi rA
Example
initi r6
Description
Ignoring the tag, initi identifies the instruction cache line
associated with the byte address in ra, and initi invalidates
that line.
If the Nios II processor core does not have an instruction cache,
the initi instruction performs no operation.
Usage
This instruction is used to initialize the processor’s instruction
cache. Immediately after processor reset, use initi to
invalidate each line of the instruction cache.
For more information on instruction cache, refer to the Cache
and Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
Exceptions
Supervisor-only instruction
Instruction Type
R
Instruction Fields
A = Register index of operand rA
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A 0 0 0x29
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
8-46
initi
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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