Specifications

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A 0 0 0x04
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x04 0 0x3a
initd
Instruction initialize data cache line
Operation
Initializes the data cache line associated with address
rA + σ(IMM16).
Assembler Syntax
initd IMM16(rA)
Example
initd 0(r6)
Description
If the Nios II processor implements a direct mapped data
cache, initd clears the data cache line without checking for (or
writing) a dirty data cache line that is mapped to the specified
address back to memory. Unlike initda, initd clears the cache
line regardless of whether the addressed data is currently
cached. This process comprises the following steps:
• Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
• Identify the data cache line associated with the computed
effective address. Each data cache effective address
comprises a tag field and a line field. When identifying the
line, initd ignores the tag field and only uses the line field
to select the data cache line to clear.
• Skip comparing the cache line tag with the effective address
to determine if the addressed data is currently cached.
Because initd ignores the cache line tag, initd flushes the
cache line regardless of whether the specified data location is
currently cached.
• Skip checking if the data cache line is dirty. Because initd
skips the dirty cache line check, data that has been modified
by the processor, but not yet written to memory is lost.
• Clear the valid bit for the line.
If the Nios II processor core does not have a data cache, the
initd instruction performs no operation.
NII51017
2015.04.02
initd
8-43
Instruction Set Reference
Altera Corporation
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