Specifications

Description
Ignoring the tag, flushi identifies the instruction cache line
associated with the byte address in rA, and invalidates that line.
If the Nios II processor core does not have an instruction cache,
the flushi instruction performs no operation.
For more information about the data cache, refer to the Cache
and Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
Exceptions
None
Instruction Type
R
Instruction Fields
A = Register index of operand rA
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A 0 0 0x0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0c 0 0x3a
Related Information
Cache and Tightly-Coupled Memory
flushp
Instruction
flush pipeline
Operation
Flushes the processor pipeline of any prefetched instructions.
Assembler Syntax
flushp
Example
flushp
Description
Ensures that any instructions prefetched after the flushp
instruction are removed from the pipeline.
Usage
Use flushp before transferring control to newly updated
instruction memory.
Exceptions
None
Instruction Type
R
Instruction Fields
None
8-42
flushp
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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