Specifications

Bit Fields
IMM16 0x3b
Related Information
• Cache and Tightly-Coupled Memory
• flushda on page 8-40
• initda on page 8-44
• initd on page 8-43
flushda
Instruction
flush data cache address
Operation
Flushes the data cache line currently caching address
rA + σ(IMM16)
Assembler Syntax
flushda IMM16(rA)
Example
flushda -100(r6)
Description
If the Nios II processor implements a direct mapped data
cache, flushda writes the data cache line that is mapped to the
specified address back to memory if the line is dirty, and then
clears the data cache line. Unlike flushd, flushda writes the
dirty data back to memory only when the addressed data is
currently in the cache. This process comprises the following
steps:
• Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
• Identify the data cache line associated with the computed
effective address. Each data cache effective address
comprises a tag field and a line field. When identifying the
line, flushda uses both the tag field and the line field.
• Compare the cache line tag with the effective address to
determine if the addressed data is currently cached. If the
tag fields do not match, the effective address is not
currently cached, so the instruction does nothing.
• If the data cache line is dirty and the tag fields match, write
the dirty cache line back to memory. A cache line is dirty
when one or more words of the cache line have been
modified by the processor, but are not yet written to
memory.
• Clear the valid bit for the line.
If the Nios II processor core does not have a data cache, the
flushda instruction performs no operation.
8-40
flushda
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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