Specifications

Feature Floating-Point Hardware
Implementation with IEEE 754-
1985
Floating-Point Hardware 2
Implementation with IEEE 754-
2008
NaN
Quiet Implemented
No distinction is made
between signaling and quiet
NaNs as input operands. A
result that produces a NaN
may produce either a
signaling or quiet NaN.
(1)
Signaling Not implemented
Subnormal
(denormalized)
numbers
Subnormal operands are
treated as zero. The floating-
point custom instructions do
not generate subnormal
numbers.
• The comparison,
minimum, maximum,
negate, and absolute
operations support
subnormal numbers.
• The add, subtract,
multiply, divide, square
root, and float to integer
operations do NOT
support subnormal
numbers. Subnormal
operands are treated as
signed zero. The
floating-point custom
instructions do not
generate subnormal
numbers.
(1)
• The integer to float
operation cannot create
subnormal numbers.
Software
exceptions
Not implemented. IEEE 754-
1985 exception conditions are
detected and handled as
described elsewhere in this
table.
Not implemented. IEEE
754-2008 exception
conditions are detected and
handled as described
elsewhere in this table.
(1)
Status flags Not implemented. IEEE 754-
1985 exception conditions are
detected and handled as
described elsewhere in this
table.
Not implemented. IEEE
754-2008 exception
conditions are detected and
handled as described
elsewhere in this table.
(1)
Note: The Floating Point Hardware 2 component also supports faithful rounding, which is not an IEEE
754-defined rounding mode. Faithful rounding rounds results to either the upper or lower nearest
single-precision numbers. Therefore, the result produced is one of two possible values and the
choice between the two is not defined. The maximum error of faithful rounding is 1 unit in the last
place (ulp). Errors may not be evenly distributed.
(1)
This operation is not fully compliant with IEEE 754-2008.
NII51002
2015.04.02
Floating-Point Instructions
2-7
Processor Architecture
Altera Corporation
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