Specifications

Description
Treating rA and rB as signed integers, this instruction divides
rA by rB and then stores the integer portion of the resulting
quotient to rC. After attempted division by zero, the value of rC
is undefined. There is no divide-by-zero exception. After
dividing –2147483648 by –1, the value of rC is undefined (the
number [phone] is not representable in 32 bits). There is
no overflow exception.
Nios II processors that do not implement the div instruction
cause an unimplemented instruction exception.
Usage
Remainder of Division:
If the result of the division is defined, then the remainder can
be computed in rD using the following instruction sequence:
div rC, rA, rB
mul rD, rC, rB
sub rD, rA, rD
# The original div operation
# rD = remainder
Exceptions
Division error
Unimplemented instruction
Instruction Type
R
Instruction Fields
A = Register index of operand rA
B = Register index of operand rB
C = Register index of operand rC
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B C 0x18
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x25 0 0x3a
divu
Instruction
divide unsigned
Operation
rC ← rA ÷ rB
Assembler Syntax
divu rC, rA, rB
Example
divu r6, r7, r8
8-36
divu
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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