Specifications

Contents
Introduction........................................................................................................ 1-1
Nios II Processor System Basics.................................................................................................................1-1
Getting Started with the Nios II Processor...............................................................................................1-2
Customizing Nios II Processor Designs................................................................................................... 1-3
Configurable Soft Processor Core Concepts............................................................................................1-4
Configurable Soft Processor Core..................................................................................................1-4
Flexible Peripheral Set and Address Map.....................................................................................1-4
Automated System Generation......................................................................................................1-5
OpenCore Plus Evaluation......................................................................................................................... 1-5
Document Revision History.......................................................................................................................1-6
Processor Architecture........................................................................................2-1
Processor Implementation..........................................................................................................................2-2
Register File...................................................................................................................................................2-3
Arithmetic Logic Unit.................................................................................................................................2-4
Unimplemented Instructions.........................................................................................................2-4
Custom Instructions........................................................................................................................2-5
Floating-Point Instructions............................................................................................................ 2-5
Reset and Debug Signals...........................................................................................................................2-10
Exception and Interrupt Controllers.......................................................................................................2-11
Exception Controller.....................................................................................................................2-11
EIC Interface...................................................................................................................................2-11
Internal Interrupt Controller....................................................................................................... 2-12
Memory and I/O Organization................................................................................................................2-12
Instruction and Data Buses.......................................................................................................... 2-14
Cache Memory...............................................................................................................................2-16
Tightly-Coupled Memory.............................................................................................................2-17
Address Map...................................................................................................................................2-18
Memory Management Unit..........................................................................................................2-18
Memory Protection Unit.............................................................................................................. 2-19
JTAG Debug Module................................................................................................................................ 2-20
JTAG Target Connection..............................................................................................................2-20
Download and Execute Software.................................................................................................2-21
Software Breakpoints.....................................................................................................................2-21
Hardware Breakpoints.................................................................................................................. 2-21
Hardware Triggers.........................................................................................................................2-21
Trace Capture.................................................................................................................................2-22
Document Revision History.....................................................................................................................2-23
Programming Model...........................................................................................3-1
Operating Modes......................................................................................................................................... 3-1
TOC-2
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