Specifications

Notation Meaning
0xNNMM Hexadecimal notation
X : Y Bitwise concatenation
For example, (0x12 : 0x34) = 0x1234
σ(X) The value of X after being sign-extended to a full register-sized signed integer
X >> n The value X after being right-shifted n bit positions
X << n The value X after being left-shifted n bit positions
X & Y Bitwise logical AND
X | Y Bitwise logical OR
X ^ Y Bitwise logical XOR
~X Bitwise logical NOT (one’s complement)
Mem8[X] The byte located in data memory at byte address X
Mem16[X] The halfword located in data memory at byte address X
Mem32[X] The word located in data memory at byte address X
label An address label specified in the assembly file
(signed) rX The value of rX treated as a signed number
(unsigned) rX The value of rX treated as an unsigned number
Note: All register operations apply to the current register set, except as noted.
The following exceptions are not listed for each instruction because they can occur on any instruction
fetch:
• Supervisor-only instruction address
• Fast TLB miss (instruction)
• Double TLB miss (instruction)
• TLB permission violation (execute)
• MPU region violation (instruction)
For information about these and all Nios II exceptions, refer to the Programming Model chapter of the
Nios II Processor Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
add
Instruction
add
Operation
rC ← rA + rB
Assembler Syntax
add rC, rA, rB
8-6
add
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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