Specifications

Nios II/s Core
Table 6-4: Nios II/s Core Revisions
Version Release Date Notes
13.1 November
2013
• Added support for enhanced floating-point custom instructions
11.0 May 2011 No changes.
10.1 December
2010
No changes.
10.0 July 2010 No changes.
9.1 November
2009
No changes.
9.0 March 2009 No changes.
8.1 November
2008
No changes.
8.0 May 2008 Implemented the illegal instruction exception.
7.2 October 2007 Implemented the jmpi instruction.
7.1 May 2007 No changes.
7.0 March 2007 No changes.
6.1 November
2006
No changes.
6.0 May 2006 Cycle count for flushi and initi instructions changes from 1 to 4
cycles.
5.1 October 2005 No changes.
5.0 May 2005
• Added optional tightly-coupled memory ports. Designers can add
zero to four tightly-coupled instruction master ports.
• Made instruction cache optional (previously instruction cache was
always present). If the instruction cache is not present, the Nios II
core does not have an instruction master port, and must use a
tightly-coupled instruction memory.
• Support for HardCopy devices (previous versions required a
workaround to support HardCopy devices).
6-6
Nios II/s Core
NII51018
2015.04.02
Altera Corporation
Nios II Processor Revision History
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