Specifications

Architecture Revisions
Architecture revisions augment the fundamental capabilities of the Nios II architecture, and affect all
Nios II cores. A change in the architecture mandates a revision to all Nios II cores to accommodate the
new architectural enhancement. For example, when Altera adds a new instruction to the instruction set,
Altera consequently must update all Nios II cores to recognize the new instruction.
Table 6-2: Nios II Architecture Revisions
Version Release Date Notes
13.1 November
2013
• Added ECC support for internal RAM blocks (instruction cache,
MMU TLB, and register file)
• Added support for enhanced floating-point custom instructions
11.0 May 2011 No changes.
10.1 December
2010
No changes.
10.0 July 2010 No changes.
9.1 November
2009
• Added optional external interrupt controller interface.
• Added optional shadow register sets.
9.0 March 2009 No changes.
8.1 November
2008
No changes.
8.0 May 2008
• Added an optional MMU.
• Added an optional MPU.
• Added advanced exception checking to detect division errors,
illegal instructions, misaligned memory accesses, and provide extra
exception information.
• Added the initda instruction.
7.2 October 2007 Added the jmpi instruction.
7.1 May 2007 No changes.
7.0 March 2007 No changes.
6.1 November
2006
No changes.
6.0 May 2006 Added optional cpu_resetrequest and cpu_resettaken signals to all
processor cores.
5.1 October 2005 No changes.
5.0 May 2005 Added the flushda instruction.
1.1 December
2004
• Added cpuid control register.
• Updated break instruction specification to accept an immediate
argument for use by debugging tools.
NII51018
2015.04.02
Architecture Revisions
6-3
Nios II Processor Revision History
Altera Corporation
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