Specifications

Version Release Date Notes
9.1 November
2009
• Added optional external interrupt controller interface.
• Added optional shadow register sets.
9.0 March 2009 No changes.
8.1 November
2008
No changes.
8.0 May 2008
• Added an optional memory management unit (MMU).
• Added an optional memory protection unit (MPU).
• Added advanced exception checking.
• Added the initda instruction.
7.2 October 2007 Added the jmpi instruction.
7.1 May 2007 No changes.
7.0 March 2007 No changes.
6.1 November
2006
No changes.
6.0 May 2006 The name Nios II Development Kit describing the software develop‐
ment tools changed to Nios II Embedded Design Suite.
5.1 SP1 January 2006 Bug fix for Nios II/f core.
5.1 October 2005 No changes.
5.0 May 2005
• Changed version nomenclature. Altera now aligns the Nios II
processor version with Altera's Quartus
®
II software version.
• Memory structure enhancements:
(1) Added tightly-coupled memory.
(2) Made data cache line size configurable.
(3) Made cache optional in Nios II/f and Nios II/s cores.
• Support for HardCopy
®
devices.
1.1 December
2004
• Minor enhancements to the architecture: Added cpuid control
register, and updated the break instruction.
• Increased user control of multiply and shift hardware in the
arithmetic logic unit (ALU) for Nios II/s and Nios II/f cores.
• Minor bug fixes.
1.01 September
2004
• Minor bug fixes.
1.0 May2004 Initial release of the Nios II processor.
6-2
Nios II Versions
NII51018
2015.04.02
Altera Corporation
Nios II Processor Revision History
Send Feedback