Specifications

Nios II Processor Revision History
6
2015.04.02
NII51018
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Each release of the Nios
®
II Embedded Design Suite (EDS) introduces improvements to the Nios II
processor, the software development tools, or both. This chapter catalogs the history of revisions to the
Nios II processor; it does not track revisions to development tools, such as the Nios II Software Build
Tools (SBT).
Improvements to the Nios II processor might affect:
• Features of the Nios II architecture—An example of an architecture revision is adding instructions to
support floating-point arithmetic.
• Implementation of a specific Nios II core—An example of a core revision is increasing the maximum
possible size of the data cache memory for the Nios II/f core.
• Features of the JTAG debug module—An example of a JTAG debug module revision is adding an
additional trigger input to the JTAG debug module, allowing it to halt processor execution on a new
type of trigger event.
Altera implements Nios II revisions such that code written for an existing Nios II core also works on
future revisions of the same core.
Nios II Versions
The number for any version of the Nios II processor is determined by the version of the Nios II EDS. For
example, in the Nios II EDS version 8.0, all Nios II cores are also version 8.0.
Table 6-1: Nios II Processor Revision History
Version Release Date Notes
13.1 November
2013
• Added ECC support for internal RAM blocks (instruction cache,
MMU TLB, and register file)
• Added support for enhanced floating-point custom instructions
11.0 May 2011 No changes.
10.1 December
2010
No changes.
10.0 July 2010 No changes.
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