Specifications

Instruction Cycles Penalties
Branch (correctly predicted
taken)
2
Branch (correctly predicted
not taken)
1
Branch (mispredicted) 4 Pipeline flush
trap, break, eret, bret,
flushp, wrctl, unimple‐
mented
4 Pipeline flush
jmp, jmpi, ret, call, callr 4 Pipeline flush
rdctl 1
load, store > 1
flushi, initi 4
Multiply
Divide
Shift/rotate (with hardware
multiply using embedded
multipliers)
3
Shift/rotate (with hardware
multiply using LE-based
multipliers)
4
Shift/rotate (without
hardware multiply present)
1 to 32
All other instructions 1
Exception Handling
The Nios II/s core supports the following exception types:
• Internal hardware interrupt
• Software trap
• Illegal instruction
• Unimplemented instruction
JTAG Debug Module
The Nios II/s core supports the JTAG debug module to provide a JTAG interface to software debugging
tools. The Nios II/s core supports an optional enhanced interface that allows real-time trace data to be
routed out of the processor and stored in an external debug probe.
Nios II/e Core
The Nios II/e economy core is designed to achieve the smallest possible core size. Altera designed the
Nios II/e core with a singular design goal: reduce resource utilization any way possible, while still
maintaining compatibility with the Nios II instruction set architecture. Hardware resources are conserved
5-20
Exception Handling
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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