Specifications

Stage Letter Stage Name
M Memory
W Writeback
Up to one instruction is dispatched and/or retired per cycle. Instructions are dispatched and retired in-
order. Static branch prediction is implemented using the branch offset direction; a negative offset
(backward branch) is predicted as taken, and a positive offset (forward branch) is predicted as not taken.
The pipeline stalls for the following conditions:
• Multicycle instructions (e.g., shift/rotate without hardware multiply)
• Avalon-MM instruction master port read accesses
• Avalon-MM data master port read/write accesses
• Data dependencies on long latency instructions (e.g., load, multiply, shift operations)
Pipeline Stalls
The pipeline is set up so that if a stage stalls, no new values enter that stage or any earlier stages. No
“catching up” of pipeline stages is allowed, even if a pipeline stage is empty.
Only the M-stage is allowed to create stalls.
The M-stage stall occurs if any of the following conditions occurs:
• An M-stage load/store instruction is waiting for Avalon-MM data master transfer to complete.
• An M-stage shift/rotate instruction is still performing its operation when using the multicycle shift
circuitry (i.e., when the hardware multiplier is not available).
• An M-stage shift/rotate/multiply instruction is still performing its operation when using the hardware
multiplier (which takes three cycles).
• An M-stage multicycle custom instruction is asserting its stall signal. This only occurs if the design
includes multicycle custom instructions.
Branch Prediction
The Nios II/s core performs static branch prediction to minimize the cycle penalty associated with taken
branches.
Instruction Performance
All instructions take one or more cycles to execute. Some instructions have other penalties associated with
their execution. Instructions that flush the pipeline cause up to three instructions after them to be
cancelled. This creates a three-cycle penalty and an execution time of four cycles. Instructions that require
an Avalon-MM transfer are stalled until the transfer completes.
Table 5-15: Instruction Execution Performance for Nios II/s Core
Instruction Cycles Penalties
Normal ALU instructions
(e.g., add, cmplt)
1
Combinatorial custom
instructions
1
Multicycle custom instruc‐
tions
> 1
NII51015
2015.04.02
Pipeline Stalls
5-19
Nios II Core Implementation Details
Altera Corporation
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