Specifications

• Direct-mapped cache implementation
• The instruction master port reads an entire cache line at a time from memory, and issues one read per
clock cycle.
• Critical word first
Table 5-13: Instruction Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
tag line
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
line offset
The size of the tag field depends on the size of the cache memory and the physical address size. The size of
the line field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-
byte line). The maximum instruction byte address size is 31 bits.
The instruction cache is optional. However, excluding instruction cache from the Nios II/s core requires
that the core include at least one tightly-coupled instruction memory.
Tightly-Coupled Memory
The Nios II/s core provides optional tightly-coupled memory interfaces for instructions. A Nios II/s core
can use up to four tightly-coupled instruction memories. When a tightly-coupled memory interface is
enabled, the Nios II core includes an additional memory interface master port. Each tightly-coupled
memory interface must connect directly to exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes addresses internally to determine if
requested instructions reside in tightly-coupled memory. If the address resides in tightly-coupled
memory, the Nios II core fetches the instruction through the tightly-coupled memory interface. Software
does not require awareness of whether code resides in tightly-coupled memory or not.
Accessing tightly-coupled memory bypasses cache memory. The processor core functions as if cache were
not present for the address span of the tightly-coupled memory. Instructions for managing cache, such as
initi and flushi, do not affect the tightly-coupled memory, even if the instruction specifies an address
in tightly-coupled memory.
Execution Pipeline
This section provides an overview of the pipeline behavior for the benefit of performance-critical
applications. Designers can use this information to minimize unnecessary processor stalling. Most
application programmers never need to analyze the performance of individual instructions.
The Nios II/s core employs a 5-stage pipeline.
Table 5-14: Implementation Pipeline Stages for Nios II/s Core
Stage Letter Stage Name
F Fetch
D Decode
E Execute
5-18
Tightly-Coupled Memory
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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