Specifications

ALU Option Hardware Details Cycles per instruc‐
tion
Supported Instructions
Embedded multiplier
on Cyclone III families
ALU includes 32 x 16-bit
multiplier
5 mul, muli
Hardware divide ALU includes multicycle
divide circuit
4 – 66 div, divu
Shift and Rotate Performance
The performance of shift operations depends on the hardware multiply option. When a hardware
multiplier is present, the ALU achieves shift and rotate operations in three or four clock cycles. Otherwise,
the ALU includes dedicated shift circuitry that achieves one-bit-per-cycle shift and rotate performance.
Refer to the "Instruction Execution Performance for Nios II/s Core" table in the "Instruction Perform‐
ance" section for details.
Related Information
Instruction Performance on page 5-19
Memory Access
The Nios II/s core provides instruction cache, but no data cache. The instruction cache size is user-
definable, between 512 bytes and 64 KB. The Nios II/s core can address up to 2 GB of external memory.
The Nios II architecture reserves the most-significant bit of data addresses for the bit-31 cache bypass
method. In the Nios II/s core, bit 31 is always zero.
For information regarding data cache bypass methods, refer to the Processor Architecture chapter of the
Nios II Processor Reference Handbook.
Related Information
• Processor Architecture on page 2-1
• Processor Architecture
Instruction and Data Master Ports
The instruction master port is a pipelined Avalon Memory-Mapped (Avalon-MM) master port. If the
core includes data cache with a line size greater than four bytes, then the data master port is a pipelined
Avalon-MM master port. Otherwise, the data master port is not pipelined.
The instruction and data master ports on the Nios II/f core are optional. A master port can be excluded, as
long as the core includes at least one tightly-coupled memory to take the place of the missing master port.
Note:
Although the Nios II processor can operate entirely out of tightly-coupled memory without the
need for Avalon-MM instruction or data masters, software debug is not possible when either the
Avalon-MM instruction or data master is omitted.
Support for pipelined Avalon-MM transfers minimizes the impact of synchronous memory with pipeline
latency. The pipelined instruction and data master ports can issue successive read requests before prior
requests complete.
Instruction Cache
The instruction cache for the Nios II/s core is nearly identical to the instruction cache in the Nios II/f
core. The instruction cache memory has the following characteristics:
NII51015
2015.04.02
Shift and Rotate Performance
5-17
Nios II Core Implementation Details
Altera Corporation
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