Specifications

Overview
The Nios II/s core:
• Has an instruction cache, but no data cache
• Can access up to 2 GB of external address space
• Supports optional tightly-coupled memory for instructions
• Employs a 5-stage pipeline
• Performs static branch prediction
• Provides hardware multiply, divide, and shift options to improve arithmetic performance
• Supports the addition of custom instructions
• Supports the JTAG debug module
• Supports optional JTAG debug module enhancements, including hardware breakpoints and real-time
trace
The following sections discuss the noteworthy details of the Nios II/s core implementation. This
document does not discuss low-level design issues or implementation details that do not affect Nios II
hardware or software designers.
Arithmetic Logic Unit
The Nios II/s core provides several ALU options to improve the performance of multiply, divide, and shift
operations.
Multiply and Divide Performance
The Nios II/s core provides the following hardware multiplier options:
• DSP Block—Includes DSP block multipliers available on the target device. This option is available only
on Altera FPGAs that have DSP Blocks.
• Embedded Multipliers—Includes dedicated embedded multipliers available on the target device. This
option is available only on Altera FPGAs that have embedded multipliers.
• Logic Elements—Includes hardware multipliers built from logic element (LE) resources.
• None—Does not include multiply hardware. In this case, multiply operations are emulated in software.
The Nios II/s core also provides a hardware divide option that includes LE-based divide circuitry in the
ALU.
Including an ALU option improves the performance of one or more arithmetic instructions.
Note:
The performance of the embedded multipliers differ, depending on the target FPGA family.
Table 5-12: Hardware Multiply and Divide Details for the Nios II/s Core
ALU Option Hardware Details Cycles per instruc‐
tion
Supported Instructions
No hardware multiply
or divide
Multiply and divide
instructions generate an
exception
– None
LE-based multiplier ALU includes 32 x 4-bit
multiplier
11 mul, muli
Embedded multiplier
on Stratix III families
ALU includes 32 x 32-bit
multiplier
3 mul, muli, mulxss, mulxsu,
mulxuu
5-16
Overview
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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